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| micron m25p40 serial flash embedded memory m25p40-vmb6txx M25P40-VMC6GX; m25p40-vmc6txx m25p40-vmn3px; m25p40-vmn3txx m25p40-vmn6pxx; m25p40-vmn6txxx m25p40-vmp6gx; m25p40-vmp6txx m25p40-vms6gx; m25p40-vms6tx m25p40-vmw6gx; m25p40-vmw6txx features ? spi bus-compatible serial interface ? 4mb flash memory ? 75 mhz clock frequency (maximum) ? 2.3v to 3.6v single supply voltage ? page program (up to 256 bytes) in 0.8ms (typ) ? erase capability C sector erase: 512kb in 0.6 s (typ) C bulk erase: 4mb in 4.5 s (typ) ? write protection C hardware write protection: protected area size defined by nonvolatile bits bp0, bp1, bp2 ? deep power-down: 1a (typ) ? electronic signature C jedec-standard 2-byte signature (2013h) C unique id code (uid) with 16-byte read-only space, available upon request C res command, one-byte signature (12h) for backward compatibility ? more than 100,000 write cycles per sector ? automotive-grade parts available ? packages (rohs-compliant) C so8n (mn) 150 mils C so8w (mw) 208 mils C dfn8 (ms) mlp8, 6mm x 5mm C vfdfpn8 (mp) mlp8 6mm x 5mm C ufdfpn8 (mc) mlp8 4mm x 3mm C ufdfpn8 (mb) mlp8 2mm x 3mm micron m25p40 serial flash embedded memory features pdf: 09005aef8456654f m25p40.pdf - rev. y 8/12 en 1 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. products and specifications discussed herein are subject to change by micron without notice.
contents functional description ..................................................................................................................................... 6 signal descriptions ........................................................................................................................................... 8 spi modes ........................................................................................................................................................ 9 operating features ......................................................................................................................................... 11 page programming ..................................................................................................................................... 11 sector erase, bulk erase .............................................................................................................................. 11 polling during a write, program, or erase cycle ............................................................................................ 11 active power, standby power, and deep power-down .................................................................................. 11 status register ............................................................................................................................................ 12 data protection by protocol ........................................................................................................................ 12 software data protection ............................................................................................................................ 12 hardware data protection .......................................................................................................................... 12 hold condition .......................................................................................................................................... 13 configuration and memory map ..................................................................................................................... 14 memory configuration and block diagram .................................................................................................. 14 memory map C 4mb density ........................................................................................................................... 15 command set overview ................................................................................................................................. 16 write enable .............................................................................................................................................. 18 write disable ............................................................................................................................................. 19 read identification ................................................................................................................................. 20 read status register ................................................................................................................................ 22 wip bit ...................................................................................................................................................... 23 wel bit ...................................................................................................................................................... 23 block protect bits ....................................................................................................................................... 23 srwd bit ................................................................................................................................................... 23 write status register .............................................................................................................................. 24 read data bytes ......................................................................................................................................... 26 read data bytes at higher speed ............................................................................................................ 27 page program ............................................................................................................................................ 28 sector erase .............................................................................................................................................. 29 bulk erase .................................................................................................................................................. 30 deep power-down ..................................................................................................................................... 31 release from deep power-down .............................................................................................................. 32 read electronic signature .................................................................................................................... 33 power-up/down and supply line decoupling ................................................................................................. 34 power-up timing and write inhibit voltage specifications ............................................................................... 36 maximum ratings and operating conditions .................................................................................................. 37 electrical characteristics ................................................................................................................................ 38 ac characteristics .......................................................................................................................................... 40 package information ...................................................................................................................................... 48 device ordering information .......................................................................................................................... 54 standard parts ............................................................................................................................................ 54 automotive parts ........................................................................................................................................ 55 revision history ............................................................................................................................................. 56 rev. y C 8/12 ............................................................................................................................................... 56 rev. x C 04/12 ............................................................................................................................................. 56 rev. w C 03/12 ............................................................................................................................................ 56 rev. v C 02/12 ............................................................................................................................................. 56 rev. u C 09/2011 ......................................................................................................................................... 56 rev. 20.0 C 04/2010 ..................................................................................................................................... 56 micron m25p40 serial flash embedded memory features pdf: 09005aef8456654f m25p40.pdf - rev. y 8/12 en 2 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. rev. 19.0 C 02/2010 ..................................................................................................................................... 56 rev. 18.0 C 05/2009 ..................................................................................................................................... 56 rev. 17.0 C 02/2009 ..................................................................................................................................... 56 rev. 16.0 C 10/2008 ..................................................................................................................................... 57 rev. 15.0 C 12/2007 ..................................................................................................................................... 57 rev. 14.0 C 06/2007 ..................................................................................................................................... 57 rev. 13.0 C 05/2007 ..................................................................................................................................... 57 rev. 12.0 C 01/2007 ..................................................................................................................................... 57 rev. 11.0 C 12/2006 ..................................................................................................................................... 57 rev. 10.0 C 06/2006 ..................................................................................................................................... 58 rev. 9.0 C 04/2006 ....................................................................................................................................... 58 rev. 8.0 C 12/2005 ....................................................................................................................................... 58 rev. 7.0 C 10/2005 ....................................................................................................................................... 58 rev. 6.0 C 08/2005 ....................................................................................................................................... 58 rev. 5.0 C 01/2005 ....................................................................................................................................... 58 rev. 4.0 C 08/2004 ....................................................................................................................................... 58 rev. 3.0 C 03/2004 ....................................................................................................................................... 59 rev. 2.0 C 11/2003 ....................................................................................................................................... 59 rev. 1.0 C 06/2003 ....................................................................................................................................... 59 micron m25p40 serial flash embedded memory features pdf: 09005aef8456654f m25p40.pdf - rev. y 8/12 en 3 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. list of figures figure 1: logic diagram ................................................................................................................................... 6 figure 2: pin connections: so8, mlp8 ............................................................................................................. 7 figure 3: spi modes supported ........................................................................................................................ 9 figure 4: bus master and memory devices on the spi bus ............................................................................... 10 figure 5: hold condition activation ............................................................................................................... 13 figure 6: block diagram ................................................................................................................................ 14 figure 7: write enable command sequence .............................................................................................. 18 figure 8: write disable command sequence ............................................................................................. 19 figure 9: read identification command sequence ................................................................................. 21 figure 10: read status register command sequence .............................................................................. 22 figure 11: status register format ................................................................................................................... 22 figure 12: write status register command sequence ............................................................................. 24 figure 13: read data bytes command sequence ........................................................................................ 26 figure 14: read data bytes at higher speed command sequence ........................................................... 27 figure 15: page program command sequence ........................................................................................... 28 figure 16: sector erase command sequence ............................................................................................. 29 figure 17: bulk erase command sequence ................................................................................................. 30 figure 18: deep power-down command sequence ................................................................................... 31 figure 19: release from deep power-down command sequence ............................................................. 32 figure 20: read electronic signature command sequence .................................................................. 33 figure 21: power-up timing .......................................................................................................................... 35 figure 22: ac measurement i/o waveform ..................................................................................................... 40 figure 23: serial input timing ........................................................................................................................ 46 figure 24: write protect setup and hold during wrsr when srwd=1 timing ................................................. 46 figure 25: hold timing .................................................................................................................................. 47 figure 26: output timing .............................................................................................................................. 47 figure 27: so8n 150 mils body width ............................................................................................................ 48 figure 28: so8w 208 mils body width ............................................................................................................ 49 figure 29: dfn8 6mm x 5mm ........................................................................................................................ 50 figure 30: vfdfpn8 (mlp8) 6mm x 5mm ...................................................................................................... 51 figure 31: ufdfpn8 (mlp8) 4mm x 3mm ...................................................................................................... 52 figure 32: ufdfpn8 (mlp8) 2mm x 3mm ...................................................................................................... 53 micron m25p40 serial flash embedded memory features pdf: 09005aef8456654f m25p40.pdf - rev. y 8/12 en 4 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. list of tables table 1: signal names ...................................................................................................................................... 7 table 2: signal descriptions ............................................................................................................................. 8 table 3: protected area sizes .......................................................................................................................... 12 table 4: sectors[7:0] ...................................................................................................................................... 15 table 5: command set codes ........................................................................................................................ 17 table 6: read identification data out sequence ..................................................................................... 20 table 7: status register protection modes ...................................................................................................... 24 table 8: power-up timing and v wi threshold ................................................................................................. 36 table 9: absolute maximum ratings .............................................................................................................. 37 table 10: operating conditions ...................................................................................................................... 37 table 11: data retention and endurance ........................................................................................................ 37 table 12: dc current specifications (device grade 6) ..................................................................................... 38 table 13: dc voltage specifications (device grade 6) ...................................................................................... 38 table 14: dc current specifications (device grade 3) ..................................................................................... 38 table 15: dc voltage specifications (device grade 3) ...................................................................................... 39 table 16: device grade and ac table correlation ............................................................................................ 40 table 17: ac measurement conditions ........................................................................................................... 40 table 18: capacitance .................................................................................................................................... 40 table 19: instruction times, process technology 110nm ................................................................................. 41 table 20: instruction times, process technology 150nm ................................................................................. 41 table 21: ac specifications (25 mhz, device grade 3, v cc [min]=2.7v) ............................................................. 41 table 22: ac specifications (50 mhz, device grade 6, v cc [min]=2.7v) ............................................................. 42 table 23: ac specifications (40 mhz, device grade 6, v cc [min]=2.3v) ............................................................. 43 table 24: ac specifications (75mhz, device grade 3 and 6, v cc [min]=2.7v) .................................................... 45 table 25: part number example ..................................................................................................................... 54 table 26: part number information scheme ................................................................................................... 54 table 27: part number example ..................................................................................................................... 55 table 28: part number information scheme ................................................................................................... 55 micron m25p40 serial flash embedded memory features pdf: 09005aef8456654f m25p40.pdf - rev. y 8/12 en 5 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. functional description the m25p40 is an 4mb (512kb x 8) serial flash memory device with advanced write- protection mechanisms accessed by a high-speed spi-compatible bus. the device sup- ports high-performance commands for clock frequency up to 75mhz. the memory can be programmed 1 to 256 bytes at a time using the page program command. it is organized as 8 sectors, each containing 256 pages. each page is 256 bytes wide. the entire memory can be erased using the bulk erase command, or it can be erased one sector at a time using the sector erase command. this data sheet details the functionality of the m25p40 device based on either the 150nm process or on the current 110nm process. the most current device in the 110nm process has the following additional features and is completely backward compatible with the 150nm device: ? maximum frequency (read data bytes at higher speed operation) in the stand- ard v cc range 2.7v to 3.6v equals 75mhz ? maximum frequency (read data bytes at higher speed operation) in the exten- ded v cc range 2.3v to 2.7v equals 40mhz ? uid/cfd protection feature note: 75mhz operation is available only on the v cc range 2.7v to 3.6v and for 110nm process technology devices, identified by process identification digit 4 in the device marking and process letter b in the part number. figure 1: logic diagram s# v cc hold# v ss dq1 c dq0 w# micron m25p40 serial flash embedded memory functional description pdf: 09005aef8456654f m25p40.pdf - rev. y 8/12 en 6 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. table 1: signal names signal name function direction c serial clock input dq0 serial data input input dq1 serial data output output s# chip select input w# write protect or enhanced program supply voltage input hold# hold input v cc supply voltage C v ss ground C figure 2: pin connections: so8, mlp8 1 2 3 4 v cc hold# 5 6 7 8 dq1 v ss s# dq0 c w# there is an exposed central pad on the underside of the mlp8 package that is pulled internally to v ss , and must not be connected to any other voltage or signal line on the pcb. the package mechanical section provides information on package dimensions and how to identify pin 1. micron m25p40 serial flash embedded memory functional description pdf: 09005aef8456654f m25p40.pdf - rev. y 8/12 en 7 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. signal descriptions table 2: signal descriptions signal type description dq1 output serial data: the dq1 output signal is used to transfer data serially out of the device. data is shifted out on the falling edge of the serial clock (c). dq0 input serial data: the dq0 input signal is used to transfer data serially into the device. it receives commands, addresses, and the data to be programmed. values are latched on the rising edge of the serial clock (c). c input clock: the c input signal provides the timing of the serial interface. commands, ad- dresses, or data present at serial data input (dq0) is latched on the rising edge of the serial clock (c). data on dq1 changes after the falling edge of c. s# input chip select: when the s# input signal is high, the device is deselected and dq1 is at high impedance. unless an internal program, erase, or write status register cy- cle is in progress, the device will be in the standby power mode (not the deep power- down mode). driving s# low enables the device, placing it in the active power mode. after power-up, a falling edge on s# is required prior to the start of any com- mand. hold# input hold: the hold# signal is used to pause any serial communications with the device without deselecting the device. during the hold condition, dq1 is high-z. dq0 and c are "dont care." to start the hold condition, the device must be selected, with s# driven low. w# input write protect: the w# input signal is used to freeze the size of the area of memory that is protected against program or erase commands as specified by the values in bp2, bp1, and bp0 bits of the status register. v cc input device core power supply: source voltage. v ss input ground: reference for the v cc supply voltage. micron m25p40 serial flash embedded memory signal descriptions pdf: 09005aef8456654f m25p40.pdf - rev. y 8/12 en 8 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. spi modes these devices can be driven by a microcontroller with its serial peripheral interface (spi) running in either of the following two spi modes: ? cpol=0, cpha=0 ? cpol=1, cpha=1 for these two modes, input data is latched in on the rising edge of serial clock (c), and output data is available from the falling edge of c. the difference between the two modes is the clock polarity when the bus master is in standby mode and not transferring data: ? c remains at 0 for (cpol=0, cpha=0) ? c remains at 1 for (cpol=1, cpha=1) figure 3: spi modes supported c msb cpha dq0 0 1 cpol 0 1 dq1 c msb because only one device is selected at a time, only one device drives the serial data out- put (dq1) line at a time, while the other devices are high-z. an example of three devi- ces connected to an mcu on an spi bus is shown here. micron m25p40 serial flash embedded memory spi modes pdf: 09005aef8456654f m25p40.pdf - rev. y 8/12 en 9 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. figure 4: bus master and memory devices on the spi bus spi bus master spi memory device sdo sdi sck c dq1 dq0 s# spi memory device c dq1 dq0 s# spi memory device c dq1 dq0 s# cs3 cs2 cs1 spi interface with (cpol, cpha) = (0, 0) or (1, 1) w# hold# hold# w# hold# r r r v cc v cc v cc v cc v ss v ss v ss v ss r w# notes: 1. write protect (w#) and hold# should be driven high or low as appropriate. 2. resistors (r) ensure that the memory device is not selected if the bus master leaves the s# line high-z. 3. the bus master may enter a state where all i/o are high-z at the same time; for exam- ple, when the bus master is reset. therefore, the c must be connected to an external pull-down resistor so that when all i/o are high-z, s# is pulled high while c is pulled low. this ensures that s# and c do not go high at the same time and that the t shch requirement is met. 4. the typical value of r is 100 k , assuming that the time constant r c p (c p = parasitic capacitance of the bus line) is shorter than the time during which the bus master leaves the spi bus high-z. 5. example: given that c p = 50 pf (r c p = 5 s), the application must ensure that the bus master never leaves the spi bus high-z for a time period shorter than 5 s. micron m25p40 serial flash embedded memory spi modes pdf: 09005aef8456654f m25p40.pdf - rev. y 8/12 en 10 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. operating features page programming to program one data byte, two commands are required: write enable, which is one byte, and a page program sequence, which is four bytes plus data. this is followed by the internal program cycle of duration t pp . to spread this overhead, the page pro- gram command allows up to 256 bytes to be programmed at a time (changing bits from 1 to 0), provided they lie in consecutive addresses on the same page of memory. to optimize timings, it is recommended to use the page program command to program all consecutive targeted bytes in a single sequence than to use several page program sequences with each containing only a few bytes. sector erase, bulk erase the page program command allows bits to be reset from 1 to 0. before this can be applied, the bytes of memory need to have been erased to all 1s (ffh). this can be ach- ieved a sector at a time using the sector erase command, or throughout the entire memory using the bulk erase command. this starts an internal erase cycle of dura- tion t sse , t se or t be . the erase command must be preceded by a write enable com- mand. polling during a write, program, or erase cycle an improvement in the time to complete the following commands can be achieved by not waiting for the worst case delay (t w , t pp , t se , or t be ). ? write status register ? program ? erase (sector erase, bulk erase) the write in progress (wip) bit is provided in the status register so that the application program can monitor this bit in the status register, polling it to establish when the pre- vious write cycle, program cycle, or erase cycle is complete. active power, standby power, and deep power-down when chip select (s#) is low, the device is selected, and in the active power mode. when s# is high, the device is deselected, but could remain in the active power mode until all internal cycles have completed (program, erase, write status register). the device then goes in to the standby power mode. the device con- sumption drops to i cc1 . the deep power-down mode is entered when the deep power-down command is executed. the device consumption drops further to i cc2 . the device remains in this mode until the release from deep power-down command is executed. while in the deep power-down mode, the device ignores all write, program, and erase commands. this provides an extra software protection mechanism when the device is not in active use, by protecting the device from inadvertent write, program, or erase operations. for further information, see the deep power down command. micron m25p40 serial flash embedded memory operating features pdf: 09005aef8456654f m25p40.pdf - rev. y 8/12 en 11 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. status register the status register contains a number of status and control bits that can be read or set (as appropriate) by specific commands. for a detailed description of the status register bits, see read status register (page 22). data protection by protocol non-volatile memory is used in environments that can include excessive noise. the fol- lowing capabilities help protect data in these noisy environments. power on reset and an internal timer (t puw ) can provide protection against inadvertent changes while the power supply is outside the operating specification. write, program, and write status register commands are checked before they are accepted for execution to ensure they consist of a number of clock pulses that is a multiple of eight. all commands that modify data must be preceded by a write enable command to set the write enable latch (wel) bit. in addition to the low power consumption feature, the deep power-down mode of- fers extra software protection since all write, program, and erase commands are ignored when the device is in this mode. software data protection memory can be configured as read-only using the block protect bits (bp2, bp1, bp0) as shown in the protected area sizes table. hardware data protection hardware data protection is implemented using the write protect signal applied on the w# pin. this freezes the status register in a read-only mode. in this mode, the block pro- tect (bp) bits and the status register write disable bit (srwd) are protected. table 3: protected area sizes status register content memory content bp bit 2 bp bit 1 bp bit 0 protected area unprotected area 0 0 0 none all sectors (sectors 0 to 7) 0 0 1 upper 8th (sectors 7) lower 7/8ths (sectors 0 to 6) 0 1 0 upper 4th (sectors 6 and 7) lower 3/4ths (sectors 0 to 5) 0 1 1 upper half (sectors 4 to 7) lower half (sectors 0 to 3) 1 0 0 all sectors (sectors 0 to 7) none 1 0 1 all sectors (sectors 0 to 7) none 1 1 0 all sectors (sectors 0 to 7) none 1 1 1 all sectors (sectors 0 to 7) none note: 1. 0 0 0 = unprotected area (sectors): the device is ready to accept a bulk erase command only if all block protect bits (bp2, bp1, bp0) are 0. micron m25p40 serial flash embedded memory operating features pdf: 09005aef8456654f m25p40.pdf - rev. y 8/12 en 12 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. hold condition the hold# signal is used to pause any serial communications with the device without resetting the clocking sequence. however, taking this signal low does not terminate any write status register, program, or erase cycle that is currently in progress. to enter the hold condition, the device must be selected, with s# low. the hold condi- tion starts on the falling edge of the hold# signal, if this coincides with serial clock (c) being low. the hold condition ends on the rising edge of the hold# signal, if this co- incides with c being low. if the falling edge does not coincide with c being low, the hold condition starts after c next goes low. similarly, if the rising edge does not coin- cide with c being low, the hold condition ends after c next goes low. during the hold condition, dq1 is high impedance while dq0 and c are dont care. typically, the device remains selected with s# driven low for the duration of the hold condition. this ensures that the state of the internal logic remains unchanged from the moment of entering the hold condition. if s# goes high while the device is in the hold condition, the internal logic of the device is reset. to restart communication with the device, it is necessary to drive hold# high, and then to drive s# low. this prevents the device from going back to the hold condition. figure 5: hold condition activation hold# c hold condition (standard use) hold condition (nonstandard use) micron m25p40 serial flash embedded memory operating features pdf: 09005aef8456654f m25p40.pdf - rev. y 8/12 en 13 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. configuration and memory map memory configuration and block diagram each page of memory can be individually programmed; bits are programmed from 1 to 0. the device is sector or bulk-erasable, but not page-erasable; bits are erased from 0 to 1. the memory is configured as follows: ? 524,288 bytes (8 bits each) ? 8 sectors (512kb, 65kb each) ? 2048 pages (256 bytes each) figure 6: block diagram hold# s# w# control logic high voltage generator i/o shift register address register and counter 256 byte data buffer 256 bytes (page size) x decoder y decoder c dq0 dq1 status register 00000h 7ffffh 000ffh micron m25p40 serial flash embedded memory configuration and memory map pdf: 09005aef8456654f m25p40.pdf - rev. y 8/12 en 14 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. memory map C 4mb density table 4: sectors[7:0] sector address range start end 7 0007 0000h 0007 ffffh 6 0006 0000h 0006 ffffh 5 0005 0000h 0005 ffffh 4 0004 0000h 0004 ffffh 3 0003 0000h 0003 ffffh 2 0002 0000h 0002 ffffh 1 0001 0000h 0001 ffffh 0 0000 0000h 0000 ffffh micron m25p40 serial flash embedded memory memory map C 4mb density pdf: 09005aef8456654f m25p40.pdf - rev. y 8/12 en 15 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. command set overview all commands, addresses, and data are shifted in and out of the device, most significant bit first. serial data inputs dq0 and dq1 are sampled on the first rising edge of serial clock (c) after chip select (s#) is driven low. then, the one-byte command code must be shifted in to the device, most significant bit first, on dq0 and dq1, each bit being latched on the rising edges of c. every command sequence starts with a one-byte command code. depending on the command, this command code might be followed by address or data bytes, by address and data bytes, or by neither address or data bytes. for the following commands, the shifted-in command sequence is followed by a data-out sequence. s# can be driven high after any bit of the data-out sequence is being shifted out. ? read data bytes (read) ? read data bytes at higher speed ? read status register ? read identification ? release from deep power-down for the following commands, s# must be driven high exactly at a byte boundary. that is, after an exact multiple of eight clock pulses following s# being driven low, s# must be driven high. otherwise, the command is rejected and not executed. ? page program ? sector erase ? bulk erase ? write status register ? write enable ? write disable all attempts to access the memory array are ignored during a write status register command cycle, a program command cycle, or an erase command cycle. in addi- tion, the internal cycle for each of these commands continues unaffected. micron m25p40 serial flash embedded memory command set overview pdf: 09005aef8456654f m25p40.pdf - rev. y 8/12 en 16 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. table 5: command set codes command name one-byte command code bytes address dummy data write enable 0000 0110 06h 0 0 0 write disable 0000 0100 04h 0 0 0 read identification 1001 1111 9fh 0 0 1 to 20 read status register 0000 0101 05h 0 0 1 to write status register 0000 0001 01h 0 0 1 read data bytes 0000 0011 03h 3 0 1 to read data bytes at higher speed 0000 1011 0bh 3 1 1 to page program 0000 0010 02h 3 0 1 to 256 sector erase 1101 1000 d8h 3 0 0 bulk erase 1100 0111 c7h 0 0 0 deep power-down 1011 1001 b9h 0 0 0 release from deep power-down 1010 1011 abh 0 0 1 to micron m25p40 serial flash embedded memory command set overview pdf: 09005aef8456654f m25p40.pdf - rev. y 8/12 en 17 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. write enable the write enable command sets the write enable latch (wel) bit. the wel bit must be set before execution of every program, erase, and write com- mand. the write enable command is entered by driving chip select (s#) low, sending the command code, and then driving s# high. figure 7: write enable command sequence dont care dq[0] 0 1 2 4 5 3 7 6 c high-z dq1 msb lsb 0 0 0 0 0 0 1 1 command bits s# micron m25p40 serial flash embedded memory write enable pdf: 09005aef8456654f m25p40.pdf - rev. y 8/12 en 18 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. write disable the write disable command resets the write enable latch (wel) bit. the write disable command is entered by driving chip select (s#) low, sending the command code, and then driving s# high. the wel bit is reset under the following conditions: ? power-up ? completion of any erase operation ? completion of any program operation ? completion of any write register operation ? completion of write disable operation figure 8: write disable command sequence dont care dq[0] 0 1 2 4 5 3 7 6 c high-z dq1 msb lsb 0 0 0 0 0 0 0 1 command bits s# micron m25p40 serial flash embedded memory write disable pdf: 09005aef8456654f m25p40.pdf - rev. y 8/12 en 19 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. read identification the read identification command reads the following device identification data: ? manufacturer identification (1 byte): this is assigned by jedec. ? device identification (2 bytes): this is assigned by device manufacturer; the first byte indicates memory type and the second byte indicates device memory capacity. ? a unique id code (uid) (17 bytes,16 available upon customer request): the first byte contains length of data to follow; the remaining 16 bytes contain optional customized factory data (cfd) content. table 6: read identification data out sequence manufacturer identification device identification uid memory type memory capacity cfd length cfd content 20h 20h 13h 10h 16 bytes note: 1. the cfd bytes are read-only and can be programmed with customer data upon demand. if customers do not make requests, the devices are shipped with all the cfd bytes pro- grammed to zero. a read identification command is not decoded while an erase or program cy- cle is in progress and has no effect on a cycle in progress. the read identification command must not be issued while the device is in deep power-down mode. the device is first selected by driving chip select (s#) low. then the 8-bit command code is shifted in and content is shifted out on serial data output (dq1) as follows: the 24-bit device identification that is stored in the memory, the 8-bit cfd length, followed by 16 bytes of cfd content. each bit is shifted out during the falling edge of serial clock (c). the read identification command is terminated by driving s# high at any time during data output. when s# is driven high, the device is put in the standby power mode and waits to be selected so that it can receive, decode, and execute commands. micron m25p40 serial flash embedded memory read identification pdf: 09005aef8456654f m25p40.pdf - rev. y 8/12 en 20 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. figure 9: read identification command sequence uid device identification manufacturer identification high-z dq1 msb msb d out d out d out d out lsb lsb 7 8 15 16 32 31 0 c msb dq0 lsb command msb d out d out lsb dont care micron m25p40 serial flash embedded memory read identification pdf: 09005aef8456654f m25p40.pdf - rev. y 8/12 en 21 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. read status register the read status register command allows the status register to be read. the status register may be read at any time, even while a program, erase, or write status register cycle is in progress. when one of these cycles is in progress, it is recommen- ded to check the write in progress (wip) bit before sending a new command to the de- vice. it is also possible to read the status register continuously. figure 10: read status register command sequence high-z dq1 7 8 9 10 11 12 13 14 15 0 c msb dq0 lsb command msb d out d out d out d out d out lsb d out d out d out d out dont care figure 11: status register format b7 srwd 0 0 bp2 bp1 bp0 wel wip b0 status register write protect block protect bits write enable latch bit write in progress bit micron m25p40 serial flash embedded memory read status register pdf: 09005aef8456654f m25p40.pdf - rev. y 8/12 en 22 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. wip bit the write in progress (wip) bit indicates whether the memory is busy with a write status register cycle, a program cycle, or an erase cycle. when the wip bit is set to 1, a cycle is in progress; when the wip bit is set to 0, a cycle is not in progress. wel bit the write enable latch (wel) bit indicates the status of the internal write enable latch. when the wel bit is set to 1, the internal write enable latch is set; when the wel bit is set to 0, the internal write enable latch is reset and no write status register, pro- gram, or erase command is accepted. block protect bits the block protect bits are non-volatile. they define the size of the area to be software protected against program and erase commands. the block protect bits are written with the write status register command. when one or more of the block protect bits is set to 1, the relevant memory area, as de- fined in the protected area sizes table, becomes protected against page program and sector erase commands. the block protect bits can be written provided that the hardware protected mode has not been set. the bulk erase command is execu- ted only if all block protect bits are 0. srwd bit the status register write disable (srwd) bit is operated in conjunction with the write protect (w#/v pp ) signal. when the srwd bit is set to 1 and w#/v pp is driven low, the device is put in the hardware protected mode. in the hardware protected mode, the non-volatile bits of the status register (srwd, and the block protect bits) become read- only bits and the write status register command is no longer accepted for execu- tion. micron m25p40 serial flash embedded memory read status register pdf: 09005aef8456654f m25p40.pdf - rev. y 8/12 en 23 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. write status register the write status register command allows new values to be written to the status register. before the write status register command can be accepted, a write en- able command must have been executed previously. after the write enable com- mand has been decoded and executed, the device sets the write enable latch (wel) bit. the write status register command is entered by driving chip select (s#) low, followed by the command code and the data byte on serial data input (dq0). the write status register command has no effect on b6, b5, b1 and b0 of the status register. the status register b6 and b5 are always read as 0. s# must be driven high after the eighth bit of the data byte has been latched in. if not, the write status reg- ister command is not executed. figure 12: write status register command sequence 7 8 9 10 11 12 13 14 15 0 c msb dq0 lsb command msb lsb d in d in d in d in d in d in d in d in d in as soon as s# is driven high, the self-timed write status register cycle is initi- ated; its duration is t w . while the write status register cycle is in progress, the sta- tus register may still be read to check the value of the write in progress (wip) bit. the wip bit is 1 during the self-timed write status register cycle, and is 0 when the cycle is completed. also, when the cycle is completed, the wel bit is reset. the write status register command allows the user to change the values of the block protect bits (bp2, bp1, bp0). setting these bit values defines the size of the area that is to be treated as read-only, as defined in the protected area sizes table. the write status register command also allows the user to set and reset the status register write disable (srwd) bit in accordance with the write protect (w#/v pp ) signal. the srwd bit and the w#/v pp signal allow the device to be put in the hardware pro- teced (hpm) mode. the write status register command is not executed once the hpm is entered. the options for enabling the status register protection modes are summarized here. table 7: status register protection modes w#/v pp signal srwd bit protection mode (pm) status register write protection memory content notes protected area unprotected area 1 0 software protected mode (spm) software protection commands not accepted commands accepted 1, 2, 3 0 0 1 1 micron m25p40 serial flash embedded memory write status register pdf: 09005aef8456654f m25p40.pdf - rev. y 8/12 en 24 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. table 7: status register protection modes (continued) w#/v pp signal srwd bit protection mode (pm) status register write protection memory content notes protected area unprotected area 0 1 hardware protected mode (hpm) hardware protection commands not accepted commands accepted 3, 4, 5, notes: 1. software protection: status register is writable (srwd, bp2, bp1, and bp0 bit values can be changed) if the write enable command has set the wel bit. 2. page program, sector erase, and bulk erase commands are not accepted. 3. page program and sector erase commands can be accepted. 4. hardware protection: status register is not writable (srwd, bp2, bp1, and bp0 bit values cannot be changed). 5. page program, sector erase, and bulk erase commands are not accepted. when the srwd bit of the status register is 0 (its initial delivery state), it is possible to write to the status register provided that the wel bit has been set previously by a write enable command, regardless of whether the w#/v pp signal is driven high or low. when the status register srwd bit is set to 1, two cases need to be considered depend- ing on the state of the w#/v pp signal: ? if the w#/v pp signal is driven high, it is possible to write to the status register provi- ded that the wel bit has been set previously by a write enable command. ? if the w#/v pp signal is driven low, it is not possible to write to the status register even if the wel bit has been set previously by a write enable command. therefore, at- tempts to write to the status register are rejected, and are not accepted for execution. the result is that all the data bytes in the memory area that have been put in spm by the status register block protect bits (bp2, bp1, bp0) are also hardware protected against data modification. regardless of the order of the two events, the hpm can be entered in either of the fol- lowing ways: ? setting the status register srwd bit after driving the w#/v pp signal low ? driving the w#/v pp signal low after setting the status register srwd bit. the only way to exit the hpm is to pull the w#/v pp signal high. if the w#/v pp signal is permanently tied high, the hpm can never be activated. in this case, only the spm is available, using the status register block protect bits (bp2, bp1, bp0). micron m25p40 serial flash embedded memory write status register pdf: 09005aef8456654f m25p40.pdf - rev. y 8/12 en 25 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. read data bytes the device is first selected by driving chip select (s#) low. the command code for read data bytes is followed by a 3-byte address (a23-a0), each bit being latched-in during the rising edge of serial clock (c). then the memory contents at that address is shifted out on serial data output (dq1), each bit being shifted out at a maximum fre- quency f r during the falling edge of c. the first byte addressed can be at any location. the address is automatically incremen- ted to the next higher address after each byte of data is shifted out. therefore, the entire memory can be read with a single read data bytes command. when the highest ad- dress is reached, the address counter rolls over to 000000h, allowing the read sequence to be continued indefinitely. the read data bytes command is terminated by driving s# high. s# can be driven high at any time during data output. any read data bytes command issued while an erase, program, or write cycle is in progress is rejected without any effect on the cycle that is in progress. figure 13: read data bytes command sequence dont care msb dq[0] lsb command a[max] a[min] 7 8 c x 0 c high-z dq1 msb d out d out d out d out d out lsb d out d out d out d out note: 1. cx = 7 + (a[max] + 1). micron m25p40 serial flash embedded memory read data bytes pdf: 09005aef8456654f m25p40.pdf - rev. y 8/12 en 26 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. read data bytes at higher speed the device is first selected by driving chip select (s#) low. the command code for the read data bytes at higher speed command is followed by a 3-byte address (a23- a0) and a dummy byte, each bit being latched-in during the rising edge of serial clock (c). then the memory contents at that address are shifted out on serial data output (dq1) at a maximum frequency f c , during the falling edge of c. the first byte addressed can be at any location. the address is automatically incremen- ted to the next higher address after each byte of data is shifted out. therefore, the entire memory can be read with a single read data bytes at higher speed command. when the highest address is reached, the address counter rolls over to 000000h, allow- ing the read sequence to be continued indefinitely. the read data bytes at higher speed command is terminated by driving s# high. s# can be driven high at any time during data output. any read data bytes at higher speed command issued while an erase, program, or write cycle is in progress is rejected without any effect on the cycle that is in progress. figure 14: read data bytes at higher speed command sequence 7 8 c x 0 c msb dq0 lsb command a[max] a[min] msb d out d out d out d out d out lsb d out d out d out d out dummy cycles dq1 high-z dont care note: 1. cx = 7 + (a[max] + 1). micron m25p40 serial flash embedded memory read data bytes at higher speed pdf: 09005aef8456654f m25p40.pdf - rev. y 8/12 en 27 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. page program the page program command allows bytes in the memory to be programmed, which means the bits are changed from 1 to 0. before a page program command can be ac- cepted a write enable command must be executed. after the write enable com- mand has been decoded, the device sets the write enable latch (wel) bit. the page program command is entered by driving chip select (s#) low, followed by the command code, three address bytes, and at least one data byte on serial data input (dq0). if the eight least significant address bits (a7-a0) are not all zero, all transmitted data that goes beyond the end of the current page are programmed from the start address of the same page; that is, from the address whose eight least significant bits (a7-a0) are all zero. s# must be driven low for the entire duration of the sequence. if more than 256 bytes are sent to the device, previously latched data are discarded and the last 256 data bytes are guaranteed to be programmed correctly within the same page. if less than 256 data bytes are sent to device, they are correctly programmed at the requested addresses without any effects on the other bytes of the same page. for optimized timings, it is recommended to use the page program command to program all consecutive targeted bytes in a single sequence rather than to use several page program sequences, each containing only a few bytes. s# must be driven high after the eighth bit of the last data byte has been latched in. otherwise the page program command is not executed. as soon as s# is driven high, the self-timed page program cycle is initiated; the cy- cles's duration is t pp . while the page program cycle is in progress, the status register may be read to check the value of the write in progress (wip) bit. the wip bit is 1 during the self-timed page program cycle, and 0 when the cycle is completed. at some un- specified time before the cycle is completed, the write enable latch (wel) bit is reset. a page program command is not executed if it applies to a page protected by the block protect bits bp2, bp1, and bp0. figure 15: page program command sequence 7 8 c x 0 c msb dq[0] lsb command a[max] a[min] msb d in d in d in d in d in lsb d in d in d in d in note: 1. cx = 7 + (a[max] + 1). micron m25p40 serial flash embedded memory page program pdf: 09005aef8456654f m25p40.pdf - rev. y 8/12 en 28 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. sector erase the sector erase command sets to 1 (ffh) all bits inside the chosen sector. before the sector erase command can be accepted, a write enable command must have been executed previously. after the write enable command has been decoded, the device sets the write enable latch (wel) bit. the sector erase command is entered by driving chip select (s#) low, followed by the command code, and three address bytes on serial data input (dq0). any address in- side the sector is a valid address for the sector erase command. s# must be driven low for the entire duration of the sequence. s# must be driven high after the eighth bit of the last address byte has been latched in. otherwise the sector erase command is not executed. as soon as s# is driven high, the self-timed sector erase cycle is initiated; the cycle's duration is t se . while the sector erase cycle is in progress, the status register may be read to check the value of the write in progress (wip) bit. the wip bit is 1 during the self-timed sector erase cycle, and is 0 when the cycle is completed. at some unspecified time before the cycle is completed, the wel bit is reset. a sector erase command is not executed if it applies to a sector that is hardware or software protected. figure 16: sector erase command sequence 7 8 c x 0 c msb dq0 lsb command a[max] a[min] note: 1. cx = 7 + (a[max] + 1). micron m25p40 serial flash embedded memory sector erase pdf: 09005aef8456654f m25p40.pdf - rev. y 8/12 en 29 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. bulk erase the bulk erase command sets all bits to 1 (ffh). before the bulk erase command can be accepted, a write enable command must have been executed previously. af- ter the write enable command has been decoded, the device sets the write enable latch (wel) bit. the bulk erase command is entered by driving chip select (s#) low, followed by the command code on serial data input (dq0). s# must be driven low for the entire dura- tion of the sequence. s# must be driven high after the eighth bit of the command code has been latched in. otherwise the bulk erase command is not executed. as soon as s# is driven high, the self-timed bulk erase cycle is initiated; the cycle's duration is t be . while the bulk erase cycle is in progress, the status register may be read to check the value of the write in progress (wip) bit. the wip bit is 1 during the self-timed bulk erase cycle, and is 0 when the cycle is completed. at some unspecified time before the cycle is completed, the wel bit is reset. the bulk erase command is executed only if all block protect (bp2, bp1, bp0) bits are 0. the bulk erase command is ignored if one or more sectors are protected. figure 17: bulk erase command sequence 7 0 c msb dq0 lsb command micron m25p40 serial flash embedded memory bulk erase pdf: 09005aef8456654f m25p40.pdf - rev. y 8/12 en 30 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. deep power-down executing the deep power-down command is the only way to put the device in the lowest power consumption mode, the deep power-down mode. the deep power- down command can also be used as a software protection mechanism while the de- vice is not in active use because in the deep power-down mode the device ignores all write, program, and erase commands. driving chip select (s#) high deselects the device, and puts it in the standby power mode if there is no internal cycle currently in progress. once in standby power mode, the deep power-down mode can be entered by executing the deep power- down command, subsequently reducing the standby current from i cc1 to i cc2 . to take the device out of deep power-down mode, the release from deep pow- er-down command must be issued. other commands must not be issued while the device is in deep power-down mode. the deep power-down mode stops auto- matically at power-down. the device always powers up in standby power mode. the deep power-down command is entered by driving s# low, followed by the command code on serial data input (dq0). s# must be driven low for the entire dura- tion of the sequence. s# must be driven high after the eighth bit of the command code has been latched in. otherwise the deep power-down command is not executed. as soon as s# is driven high, it requires a delay of t dp before the supply current is reduced to i cc2 and the deep power-down mode is entered. any deep power-down command issued while an erase, program, or write cy- cle is in progress is rejected without any effect on the cycle that is in progress. figure 18: deep power-down command sequence 7 0 c msb dq0 lsb t dp command dont care deep power-down mode standby mode micron m25p40 serial flash embedded memory deep power-down pdf: 09005aef8456654f m25p40.pdf - rev. y 8/12 en 31 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. release from deep power-down once the device has entered deep power-down mode, all commands are ignored ex- cept release from deep power-down and read electronic signature. exe- cuting either of these commands takes the device out of the deep power-down mode. the release from deep power-down command is entered by driving chip select (s#) low, followed by the command code on serial data input (dq0). s# must be driven low for the entire duration of the sequence. the release from deep power-down command is terminated by driving s# high. sending additional clock cycles on serial clock c while s# is driven low causes the command to be rejected and not executed. after s# has been driven high, followed by a delay, t res , the device is put in the stand- by mode. s# must remain high at least until this period is over. the device waits to be selected so that it can receive, decode, and execute commands. any release from deep power-down command issued while an erase, pro- gram, or write cycle is in progress is rejected without any effect on the cycle that is in progress. figure 19: release from deep power-down command sequence high-z dq1 7 0 c msb dq0 lsb t rdp command dont care deep power-down mode standby mode micron m25p40 serial flash embedded memory release from deep power-down pdf: 09005aef8456654f m25p40.pdf - rev. y 8/12 en 32 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. read electronic signature once the device enters deep power-down mode, all commands are ignored except read electronic signature and release from deep power-down. executing either of these commands takes the device out of the deep power-down mode. the read electronic signature command is entered by driving chip select (s#) low, followed by the command code and three dummy bytes on serial data input (dq0) . each bit is latched in on the rising edge of serial clock c. the 8-bit electronic signature is shifted out on serial data output dq1 on the falling edge of c; s# must be driven low the entire duration of the sequence for the electronic signature to be read. however, driving s# high after the command code, but before the entire 8-bit electron- ic signature has been output for the first time, still ensures that the device is put into standby mode. except while an erase, program, or write status register cycle is in progress, the read electronic signature command provides access to the 8-bit electronic signature of the device, and can be applied even if deep power-down mode has not been entered. the read electronic signature command is not executed while an erase, program, or write status register cycle is in progress and has no effect on the cycle in progress. the read electronic signature command is terminated by driving s# high after the electronic signature has been read at least once. sending additional clock cycles c while s# is driven low causes the electronic signature to be output repeatedly. if s# is driven high, the device is put in standby mode immediately unless it was pre- viously in deep power-down mode. if previously in deep power-down mode, the device transitions to standby mode with delay as described here. once in standby mode, the device waits to be selected so that it can receive, decode, and execute instruc- tions. ? if s# is driven high before the electronic signature is read, transition to standby mode is delayed by tres1, as shown in the release from deep power-down com- mand sequence. s# must remain high for at least tres1(max). ? if s# is driven high after the electronic signature is read, transition to standby mode is delayed by tres2. s# must remain high for at least tres2(max). figure 20: read electronic signature command sequence 7 8 c x 0 c msb dq0 lsb command msb lsb dq1 high-z dont care d out d out d out d out d out d out d out d out dummy cycles electronic signature deep power-down standby t res2 note: 1. cx = 7 + (a[max] + 1). micron m25p40 serial flash embedded memory read electronic signature pdf: 09005aef8456654f m25p40.pdf - rev. y 8/12 en 33 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. power-up/down and supply line decoupling at power-up and power-down, the device must not be selected; that is, chip select (s#) must follow the voltage applied on v cc until v cc reaches the correct value: ? v cc,min at power-up, and then for a further delay of t vsl ? v ss at power-down a safe configuration is provided in the spi modes section. to avoid data corruption and inadvertent write operations during power-up, a power- on-reset (por) circuit is included. the logic inside the device is held reset while v cc is less than the por threshold voltage, v wi C all operations are disabled, and the device does not respond to any instruction. moreover, the device ignores the following instruc- tions until a time delay of t puw has elapsed after the moment that v cc rises above the v wi threshold: ? write enable ? page program ? sector erase ? bulk erase ? write status register however, the correct operation of the device is not guaranteed if, by this time, v cc is still below v cc.min . no write status register, program, or erase instruction should be sent until: ? t puw after v cc has passed the v wi threshold ? t vsl after v cc has passed the v cc,min level if the time, t vsl, has elapsed, after v cc rises above v cc,min , the device can be selected for read instructions even if the t puw delay has not yet fully elapsed. v pph must be applied only when v cc is stable and in the v cc,min to v cc,max voltage range. micron m25p40 serial flash embedded memory power-up/down and supply line decoupling pdf: 09005aef8456654f m25p40.pdf - rev. y 8/12 en 34 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. figure 21: power-up timing v cc v cc,min v wi reset state of the device chip selection not allowed program, erase, and write commands are rejected by the device t vsl t puw time read access allowed device fully accessible v cc,max after power-up, the device is in the following state: ? standby power mode (not the deep power-down mode) ? write enable latch (wel) bit is reset ? write in progress (wip) bit is reset ? write lock bit = 0 ? lock down bit = 0 normal precautions must be taken for supply line decoupling to stabilize the v cc sup- ply. each device in a system should have the v cc line decoupled by a suitable capacitor close to the package pins; generally, this capacitor is of the order of 100 nf. at power-down, when v cc drops from the operating voltage to below the por threshold voltage v wi , all operations are disabled and the device does not respond to any instruc- tion. note: if power-down occurs while a write, program, or erase cycle is in progress, some data corruption may result. micron m25p40 serial flash embedded memory power-up/down and supply line decoupling pdf: 09005aef8456654f m25p40.pdf - rev. y 8/12 en 35 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. power-up timing and write inhibit voltage specifications table 8: power-up timing and v wi threshold symbol parameter min max unit t vsl v cc (min) to s# low 10 C s t puw time delay to write instruction 1.0 10 ms v wi write inhibit voltage (device grade 3) 1.0 2.1 v v wi write inhibit voltage (device grade 6) 1.0 2.1 v note: 1. parameters are characterized only. if the time, t vsl , has elapsed, after v cc rises above v cc (min), the device can be selected for read instructions even if the t puw delay has not yet fully elapsed. v pph must be applied only when v cc is stable and in the v cc min to v cc max voltage range. micron m25p40 serial flash embedded memory power-up timing and write inhibit voltage specifications pdf: 09005aef8456654f m25p40.pdf - rev. y 8/12 en 36 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. maximum ratings and operating conditions caution: stressing the device beyond the absolute maximum ratings may cause perma- nent damage to the device. these are stress ratings only and operation of the device be- yond any specification or condition in the operating sections of this data sheet is not recommended. exposure to absolute maximum rating conditions for extended periods may affect device reliability. table 9: absolute maximum ratings symbol parameter min max units notes t stg storage temperature C65 150 c t lead lead temperature during soldering see note c 1 v io input and output voltage (with respect to ground) C0.6 v cc +0.6 v 2 v cc supply voltage C0.6 4.0 v v esd electrostatic discharge voltage (human body model) C2000 2000 v 3 notes: 1. the t lead signal is compliant with jedec std j-std-020c (for small body, sn-pb or pb as- sembly), the micron rohs-compliant 7191395 specification, and the european directive on restrictions on hazardous substances (rohs) 2002/95/eu. 2. the minimum voltage may reach the value of C2v for no more than 20ns during transi- tions; the maximum may reach the value of v cc +2v for no more than 20ns during tran- sitions. 3. the v esd signal: jedec std jesd22-a114a (c1 = 100 pf, r1 = 1500 , r2 = 500 ). table 10: operating conditions symbol parameter min max unit v cc supply voltage 2.3 3.6 v t a ambient operating temperature (grade 6) C40 85 c t a ambient operating temperature (grade 3) C40 125 c table 11: data retention and endurance parameter condition min max unit program/erase cycles grade 6, grade 3 100,000 C cycles per unit data retention at 55c 20 C years micron m25p40 serial flash embedded memory maximum ratings and operating conditions pdf: 09005aef8456654f m25p40.pdf - rev. y 8/12 en 37 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. electrical characteristics table 12: dc current specifications (device grade 6) symbol parameter test conditions min max units i li input leakage current C C 2 a i lo output leakage current C C 2 a i cc1 standby current s# = v cc , v in = v ss or v cc C 50 a i cc2 deep power-down current s# = v cc , v in = v ss or v cc C 10 a i cc3 operating current (read) c = 0.1v cc / 0.9v cc at 40 mhz, 50 mhz, and 75 mhz, dq1 = open C 8 ma c = 0.1v cc / 0.9v cc at 25 mhz and 33 mhz, dq1 = open C 4 ma i cc4 operating current (page program) s# = v cc C 15 ma i cc5 operating current (write status register) s# = v cc C 15 ma i cc6 operating current (sector erase) s# = v cc C 15 ma i cc7 operating current (bulk erase) s# = v cc C 15 ma table 13: dc voltage specifications (device grade 6) symbol parameter test conditions min max units v il input low voltage C C0.5 0.3v cc v v ih input high voltage C 0.7v cc v cc +0.4 v v ol output low voltage i ol = 1.6ma C 0.4 v v oh output high voltage i oh = C100a v cc C0.2 C v table 14: dc current specifications (device grade 3) symbol parameter test conditions min max units i li input leakage current C C 2 a i lo output leakage current C C 2 a i cc1 standby current s# = v cc , v in = v ss or v cc C 100 a i cc2 deep power-down current s# = v cc , v in = v ss or v cc C 50 a i cc3 operating current (read) c = 0.1v cc / 0.9v cc at 40 mhz, 50 mhz, and 75 mhz, dq1 = open C 8 ma c = 0.1v cc / 0.9v cc at 25 mhz and 33 mhz, dq1 = open C 4 ma i cc4 operating current (page program) s# = v cc C 15 ma micron m25p40 serial flash embedded memory electrical characteristics pdf: 09005aef8456654f m25p40.pdf - rev. y 8/12 en 38 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. table 14: dc current specifications (device grade 3) (continued) symbol parameter test conditions min max units i cc5 operating current (write status register) s# = v cc C 15 ma i cc6 operating current (sector erase) s# = v cc C 15 ma i cc7 operating current (bulk erase) s# = v cc C 15 ma table 15: dc voltage specifications (device grade 3) symbol parameter test conditions min max units v il input low voltage C C0.5 0.3v cc v v ih input high voltage C 0.7v cc v cc +0.4 v v ol output low voltage i ol = 1.6ma C 0.4 v v oh output high voltage i oh = C100a v cc C0.2 C v micron m25p40 serial flash embedded memory electrical characteristics pdf: 09005aef8456654f m25p40.pdf - rev. y 8/12 en 39 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. ac characteristics in the following ac specifications, output high-z is defined as the point where data out is no longer driven; however, this is not applicable to the m25px64 device. table 16: device grade and ac table correlation device grade 150nm 110nm v cc [min] f[min] ac table v cc [min] f[min] ac table grade 3 2.7v 25mhz table 21 (page 41) 2.7v 75mhz table 24 (page 45) grade 6 2.3v 40mhz table 23 (page 43) 2.3v 40mhz table 23 (page 43) grade 6 2.7v 50mhz table 22 (page 42) 2.7v 75mhz table 24 (page 45) table 17: ac measurement conditions symbol parameter min max unit c l load capacitance 30 30 pf input rise and fall times C 5 ns input pulse voltages 0.2v cc 0.8v cc v input timing reference voltages 0.3v cc 0.7v cc v output timing reference voltages v cc / 2 v cc / 2 v figure 22: ac measurement i/o waveform input and output timing reference levels input levels 0.8v cc 0.2v cc 0.7v cc 0.3v cc 0.5v cc table 18: capacitance symbol parameter test condition min max unit notes c out output capacitance (dq1) v out = 0 v C 8 pf 1 c in input capacitance (other pins) v in = 0 v C 6 pf note: 1. values are sampled only, not 100% tested, at t a =25c and a frequency of 25mhz. micron m25p40 serial flash embedded memory ac characteristics pdf: 09005aef8456654f m25p40.pdf - rev. y 8/12 en 40 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. table 19: instruction times, process technology 110nm symbol parameter min typ max units notes t w write status register cycle time C 1.3 15 ms t pp page program cycle time (256 bytes) C 0.8 5 ms 2 t pp page program cycle time ( n bytes) C int (n/8) x 0.025 t se sector erase cycle time C 0.6 3 s t be bulk erase cycle time C 4.5 10 s notes: 1. applies to the entire table: 110nm technology devices are identified by the process iden- tification digit 4 in the device marking and the process letter b in the part number. 2. when using the page program command to program consecutive bytes, optimized timings are obtained in one sequence that includes all the bytes rather than in several sequences of only a few bytes (1 < n < 256). table 20: instruction times, process technology 150nm symbol parameter min typ max units notes t w write status register cycle time C 5 15 ms t pp page program cycle time (256 bytes) C 1.4 5 ms 2 t pp page program cycle time ( n bytes) C 0.4+n*1/256 t se sector erase cycle time C 1.0 3 s t be bulk erase cycle time C 4.5 10 s notes: 1. applies to the entire table: 150nm technology devices are identified by the process iden- tification digit 4 in the device marking and the process letter b in the part number. 2. when using the page program command to program consecutive bytes, optimized timings are obtained in one sequence that includes all the bytes rather than in several sequences of only a few bytes (1 < n < 256). table 21: ac specifications (25 mhz, device grade 3, v cc [min]=2.7v) symbol alt. parameter min typ max unit notes f c f c clock frequency for commands (see note) d.c. C 25 mhz 1 f r C clock frequency for read command d.c. C 20 mhz t ch t clh clock high time 18 C C ns 2 t cl t cll clock low time 18 C C ns 2 t clch C clock rise time (peak to peak) 0.1 C C v/ns 3, 4 t chcl C clock fall time (peak to peak) 0.1 C C v/ns 3, 4 t slch t css s# active setup time (relative to c) 10 C C ns t chsl s# not active hold time (relative to c) 10 C C ns t dvch t dsu data in setup time 5 C C ns t chdx t dh data in hold time 5 C C ns t chsh C s# active hold time (relative to c) 10 C C ns t shch C s# not active setup time (relative to c) 10 C C ns micron m25p40 serial flash embedded memory ac characteristics pdf: 09005aef8456654f m25p40.pdf - rev. y 8/12 en 41 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. table 21: ac specifications (25 mhz, device grade 3, v cc [min]=2.7v) (continued) symbol alt. parameter min typ max unit notes t shsl t csh s# deselect time 100 C C ns t shqz t dis output disable time C C 15 ns 3 t clqv t v clock low to output valid C C 15 ns t clqx t ho output hold time 0 C C ns t hlch C hold# setup time (relative to c) 10 C C ns t chhh C hold# hold time (relative to c) 10 C C ns t hhch C hold# setup time (relative to c) 10 C C ns t chhl C hold# hold time (relative to c) 10 C C ns t hhqx t lz hold# to output low-z C C 15 ns 3 t hlqz t hz hold# to output high-z C C 20 ns 3 t whsl C write protect setup time 20 C C ns 5 t shwl C write protect hold time 100 C C ns 5 t dp C s# high to deep power-down mode C C 3 s 3 t res1 C s# high to standby without electronic signature read C C 30 s 3 t res2 C s# high to standby with electronic signature read C C 30 s 3 notes: 1. read data bytes at higher speed, page program, sector erase, block erase, deep power-down, read electronic signature, write enable/disable, read id, read/write status register 2. the t ch and t cl signals must be greater than or equal to 1/f c . 3. the t clch , t chcl , t shqz , t hhqx , t hlqz , t dp , t res1 , and t res2 signal values are guaranteed by characterization, not 100% tested in production. 4. the t clch and t chcl signals clock rise and fall time values are expressed as a slew-rate. 5. the t whsl and t shwl signals are only applicable as a constraint for a write status regis- ter command when srwd bit is set at 1. table 22: ac specifications (50 mhz, device grade 6, v cc [min]=2.7v) symbol alt. parameter min typ max unit notes f c f c clock frequency for commands (see note) d.c. C 50 mhz 1 f r C clock frequency for read command d.c. C 25 mhz t ch t clh clock high time 9 C C ns 2 t cl t cll clock low time 9 C C ns 2 t clch C clock rise time (peak to peak) 0.1 C C v/ns 3, 4 t chcl C clock fall time (peak to peak) 0.1 C C v/ns 3, 4 t slch t css s# active setup time (relative to c) 5 C C ns t chsl s# not active hold time (relative to c) 5 C C ns t dvch t dsu data in setup time 2 C C ns t chdx t dh data in hold time 5 C C ns t chsh C s# active hold time (relative to c) 5 C C ns t shch C s# not active setup time (relative to c) 5 C C ns micron m25p40 serial flash embedded memory ac characteristics pdf: 09005aef8456654f m25p40.pdf - rev. y 8/12 en 42 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. table 22: ac specifications (50 mhz, device grade 6, v cc [min]=2.7v) (continued) symbol alt. parameter min typ max unit notes t shsl t csh s# deselect time 100 C C ns t shqz t dis output disable time C C 8 ns 3 t clqv t v clock low to output valid C C 8 ns t clqx t ho output hold time 0 C C ns t hlch C hold# setup time (relative to c) 5 C C ns t chhh C hold# hold time (relative to c) 5 C C ns t hhch C hold# setup time (relative to c) 5 C C ns t chhl C hold# hold time (relative to c) 5 C C ns t hhqx t lz hold# to output low-z C C 8 ns 3 t hlqz t hz hold# to output high-z C C 8 ns 3 t whsl C write protect setup time 20 C C ns 5 t shwl C write protect hold time 100 C C ns 5 t dp C s# high to deep power-down mode C C 3 s 3 t res1 C s# high to standby without electronic signature read C C 30 s 3 t res2 C s# high to standby with electronic signature read C C 30 s 3 notes: 1. read data bytes at higher speed, page program, sector erase, block erase, deep power-down, read electronic signature, write enable/disable, read id, read/write status register 2. the t ch and t cl signals must be greater than or equal to 1/f c . 3. the t clch , t chcl , t shqz , t hhqx , t hlqz , t dp , t res1 , and t res2 signal values are guaranteed by characterization, not 100% tested in production. 4. the t clch and t chcl signals clock rise and fall time values are expressed as a slew-rate. 5. the t whsl and t shwl signals are only applicable as a constraint for a write status regis- ter command when srwd bit is set at 1. table 23: ac specifications (40 mhz, device grade 6, v cc [min]=2.3v) symbol alt. parameter min typ max unit notes f c f c clock frequency for commands (see note) d.c. C 40 mhz 2 f r C clock frequency for read command d.c. C 25 mhz t ch t clh clock high time 11 C C ns 3 t cl t cll clock low time 11 C C ns 3 t clch C clock rise time (peak to peak) 0.1 C C v/ns 4, 5 t chcl C clock fall time (peak to peak) 0.1 C C v/ns 4, 5 t slch t css s# active setup time (relative to c) 5 C C ns t chsl s# not active hold time (relative to c) 5 C C ns t dvch t dsu data in setup time 2 C C ns t chdx t dh data in hold time 5 C C ns t chsh C s# active hold time (relative to c) 5 C C ns t shch C s# not active setup time (relative to c) 5 C C ns micron m25p40 serial flash embedded memory ac characteristics pdf: 09005aef8456654f m25p40.pdf - rev. y 8/12 en 43 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. table 23: ac specifications (40 mhz, device grade 6, v cc [min]=2.3v) (continued) symbol alt. parameter min typ max unit notes t shsl t csh s# deselect time 100 C C ns t shqz t dis output disable time C C 8 ns 4 t clqv t v clock low to output valid C C 8 ns t clqx t ho output hold time 0 C C ns t hlch C hold# setup time (relative to c) 5 C C ns t chhh C hold# hold time (relative to c) 5 C C ns t hhch C hold# setup time (relative to c) 5 C C ns t chhl C hold# hold time (relative to c) 5 C C ns t hhqx t lz hold# to output low-z C C 8 ns 4 t hlqz t hz hold# to output high-z C C 8 ns 4 t whsl C write protect setup time 20 C C ns 6 t shwl C write protect hold time 100 C C ns 6 t dp C s# high to deep power-down mode C C 3 s 4 t res1 C s# high to standby without electronic signature read C C 30 s 4 t res2 C s# high to standby with electronic signature read C C 30 s 4 notes: 1. applies to entire table: maximum frequency in the vcc range 2.3v to 2.7v is 40mhz. 2. read data bytes at higher speed, page program, sector erase, block erase, deep power-down, read electronic signature, write enable/disable, read id, read/write status register 3. the t ch and t cl signals must be greater than or equal to 1/f c . 4. the t clch , t chcl , t shqz , t hhqx , t hlqz , t dp , t res1 , and t res2 signal values are guaranteed by characterization, not 100% tested in production. 5. the t clch and t chcl signals clock rise and fall time values are expressed as a slew-rate. 6. the t whsl and t shwl signals are only applicable as a constraint for a write status regis- ter command when srwd bit is set at 1. micron m25p40 serial flash embedded memory ac characteristics pdf: 09005aef8456654f m25p40.pdf - rev. y 8/12 en 44 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. table 24: ac specifications (75mhz, device grade 3 and 6, v cc [min]=2.7v) symbol alt. parameter min typ max unit notes f c f c clock frequency for all commands (except read) d.c. C 75 mhz f r C clock frequency for read command d.c. C 33 mhz t ch t clh clock high time 6 C C ns 3 t cl t cll clock low time 6 C C ns 3, 4 t clch C clock rise time (peak to peak) 0.1 C C v/ns 5, 6 t chcl C clock fall time (peak to peak) 0.1 C C v/ns 5, 6 t slch t css s# active setup time (relative to c) 5 C C ns t chsl s# not active hold time (relative to c) 5 C C ns t dvch t dsu data in setup time 2 C C ns t chdx t dh data in hold time 5 C C ns t chsh C s# active hold time (relative to c) 5 C C ns t shch C s# not active setup time (relative to c) 5 C C ns t shsl t csh s# deselect time 100 C C ns t shqz t dis output disable time C C 8 ns 5 t clqv t v clock low to output valid under 30 pf C C 8 ns clock low to output valid under 10 pf C C 6 ns t clqx t ho output hold time 0 C C ns t hlch C hold# setup time (relative to c) 5 C C ns t chhh C hold# hold time (relative to c) 5 C C ns t hhch C hold# setup time (relative to c) 5 C C ns t chhl C hold# hold time (relative to c) 5 C C ns t hhqx t lz hold# to output low-z C C 8 ns 5 t hlqz t hz hold# to output high-z C C 8 ns 5 t whsl C write protect setup time 20 C C ns 7 t shwl C write protect hold time 100 C C ns 7 t dp C s# high to deep power-down mode C C 3 s 5 t res1 C s# high to standby without read electronic signa- ture C C 30 s 5 t res2 C s# high to standby with read electronic signature C C 30 s 5 notes: 1. applies to entire table: 110nm technology devices are identified by the process identifi- cation digit 4 in the device marking and the process letter b in the part number. 2. applies to entire table: the ac specification values shown here are allowed only on the vcc range 2.7v to 3.6v. maximum frequency in the vcc range 2.3v to 2.7v is 40mhz. 3. the t ch and t cl signal values must be greater than or equal to 1/f c . 4. typical values are given for t a = 25c. 5. the t clch , t chcl , t shqz , t hhqx , t hlqz , t dp , and t rdp signal values are guaranteed by charac- terization, not 100% tested in production. 6. the t clch and t chcl signals clock rise and fall time values are expressed as a slew-rate. 7. the t whsl and t shwl signal values are only applicable as a constraint for a write status register command when srwd bit is set at 1. micron m25p40 serial flash embedded memory ac characteristics pdf: 09005aef8456654f m25p40.pdf - rev. y 8/12 en 45 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. figure 23: serial input timing c dq0 s# msb in dq1 tdvch high impedance lsb in tslch tchdx tchcl tclch tshch tshsl tchsh tchsl figure 24: write protect setup and hold during wrsr when srwd=1 timing c dq0 s# dq1 high impedance w#/v pp twhsl tshwl micron m25p40 serial flash embedded memory ac characteristics pdf: 09005aef8456654f m25p40.pdf - rev. y 8/12 en 46 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. figure 25: hold timing tchhl thlch thhch thhqx thlqz s# c dq1 dq0 hold# tchhh figure 26: output timing c dq1 s# lsb out dq0 address lsb in tshqz tch tcl tqlqh tqhql tclqx tclqv tclqx tclqv micron m25p40 serial flash embedded memory ac characteristics pdf: 09005aef8456654f m25p40.pdf - rev. y 8/12 en 47 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. package information figure 27: so8n 150 mils body width 8 1 0.25mm gauge plane 0.10 min/ 0.25 max 0.40 min/ 1.27 max 0 o min/ 8 o max 0.28 min/ 0.48 max 0.17 min/ 0.23 max x 45 0.25 min/ 0.50 max 0.10 max 1.75 max/ 1.27 typ 1.04 typ 1.25 min 3.90 0.10 6.00 0.20 4.90 0.10 notes: 1. the 1 that appears in the top view of the package indicates the position of pin 1. 2. drawing is not to scale. micron m25p40 serial flash embedded memory package information pdf: 09005aef8456654f m25p40.pdf - rev. y 8/12 en 48 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. figure 28: so8w 208 mils body width 8 1 0.00 min/ 0.25 max 1.51 min/ 2.00 max 5.02 min/ 6.22 max 7.62 min/ 8.89 max 0 o min/ 10 max 0.10 min/ 0.35 max 0.50 min/ 0.80 max 2.50 max 6.05 max 1.27 typ 0.40 -0.05 +0.11 0.10 max note: 1. drawing is not to scale. micron m25p40 serial flash embedded memory package information pdf: 09005aef8456654f m25p40.pdf - rev. y 8/12 en 49 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. figure 29: dfn8 6mm x 5mm 0.20 typ seating plane leads coplinarity pin 1 id laser marking 1.27 typ 3.00 0.20 0.6 +0.15 -0.1 0.02 +0.03 -0.02 0.40 +0.08 -0.05 3.00 0.20 0.90 0.10 c 6 typ pin 1 id pin 1 id option 5 typ 0.08 c 0.1 c note: 1. drawing is not to scale. micron m25p40 serial flash embedded memory package information pdf: 09005aef8456654f m25p40.pdf - rev. y 8/12 en 50 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. figure 30: vfdfpn8 (mlp8) 6mm x 5mm 12 0.20 typ 0 min/ 0.05 max 5.75 typ pin one indicator 1.27 typ 4 +0.30 -0.20 0.60 +0.15 -0.10 0.85 +0.15 -0.05 0.40 +0.08 -0.05 3.40 0.20 0.10 max/ 0 min c a b m 2x 6 typ 4.75 typ 0.05 5 typ 0.65 typ 0.10 c b 0.10 c a 0.15 c b 0.10 c a b 0.15 c a note: 1. drawing is not to scale. micron m25p40 serial flash embedded memory package information pdf: 09005aef8456654f m25p40.pdf - rev. y 8/12 en 51 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. figure 31: ufdfpn8 (mlp8) 4mm x 3mm top view b a 0.10 c 0.10 c 2x 2x bottom view side view c 0.05 c 0.10 c seating plane 0.20 dia typ 0.10 c a b 0.05 c m m datum a datum b see detail a even terminal/side datum a or b detail a terminal tip 1 2 0.127 min/ 0.15 max 0.80 typ 0.80 typ 0.40 typ 0.02 -0.02 +0.03 0.55 -0.10 +0.05 // 0.60 0.05 8 x (0.30 0.05) 0.20 0.10 4.00 0.10 0.80 0.10 8 x (0.60 0.05) 3.00 0.10 2 3 4 1 5 6 7 8 (see note 1) notes: 1. the dimension 0.30 0.05 applies to the metallic terminal and is measured between 0.15mm and 0.30mm from the terminal tip. if the terminal has the optional radius on the other end of the terminal, the dimensions should not be measured in that radius area. 2. maximum package warping is 0.05mm; maximum allowable burrs is 0.076mm in all di- rections; the bilateral coplanarity zone applies to the exposed heat sink slug as well as to the terminals. 3. drawing is not to scale. micron m25p40 serial flash embedded memory package information pdf: 09005aef8456654f m25p40.pdf - rev. y 8/12 en 52 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. figure 32: ufdfpn8 (mlp8) 2mm x 3mm 0.55 -0.10 +0.05 0.25 -0.05 +0.05 0.02 -0.02 +0.03 0.50 typ 0.15 max 0.30 min 0.08 max 2.00 -0.10 +0.10 1.60 -0.10 +0.10 3.00 -0.10 +0.10 0.20 -0.10 +0.10 0.45 -0.05 +0.05 note: 1. drawing is not to scale. micron m25p40 serial flash embedded memory package information pdf: 09005aef8456654f m25p40.pdf - rev. y 8/12 en 53 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. device ordering information standard parts for further information on line items not listed here or on any aspect of this device, contact your nearest representative. table 25: part number example part number category device type density security features operating voltage package device grade packing option plating technology lithography automotive grade m25p 40 C v mn 6 t p b a table 26: part number information scheme part number category category details notes device type m25p = serial flash memory for code storage density 40 = 4mb (512kb x 8) security features C = no extra security 1 s = cfd programmed with uid operating voltage v = v cc = 2.7v to 3.6v 2 package mn = so8n (150 mils width) mw = so8w (208 mils width) ms = dfn8 6mm x 5mm (mlp8)) 3 mp = vfdfpn8 6mm x 5mm (mlp8) mb = ufdfpn8 2mm x 3mm (mlp8) mc = ufdfpn8 4mm x 3mm (mlp8) device grade 6 = industrial temperature range: C40c to 85c. device tested with standard test flow. 3 = automotive temperature range: C40c to 125c. device tested with high reliability test flow. 4, 5 packing option C = standard packing tube t = tape and reel packing plating technology p or g = rohs compliant lithography /x = 150nm technology 6 /4 = 110nm technology, catania diffusion plant b = 110nm technology, fab 2 diffusion plant automotive grade a = automotive: C40c to 85c part. only with temperature grade 6. device tested with high reliability test flow. 4 C = automotive: C40c to 125c. only with temperature grade 3. notes: 1. secure options are available upon customer request. 2. maximum frequency device operation in the extended vcc range (2.3v to 2.7v) is only on the 40 mhz device. micron m25p40 serial flash embedded memory device ordering information pdf: 09005aef8456654f m25p40.pdf - rev. y 8/12 en 54 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. 3. exposed pad of 3mm x 3mm. 4. micron recommends the use of the automotive grade device in the automotive environ- ment, autograde 6 and grade 3. 5. device grade 3 is available in an so8 rohs compliant package. 6. identification marking /x denotes the automotive grade 3 device in 150nm technology. identification marking b denotes the 110nm technology. for additional information con- tact your nearest micron sales office. automotive parts for further information on line items not listed here or on any aspect of this device, contact your nearest representative. table 27: part number example part number category device type density security features operating voltage package device grade packing option plating technology lithography automotive grade m25p 40 C v mn 6 t p b a table 28: part number information scheme part number category category details notes device type m25p = serial flash memory for code storage density 40 = 4mb (512kb x 8) security features C = no extra security operating voltage v = v cc = 2.7v to 3.6v 1 package mn = so8n (150 mils width) mb = ufdfpn8 2mm x 3mm (mlp8) device grade 6 = industrial temperature range: C40c to 85c. device tested with high reliability test flow. 3 = automotive temperature range: C40c to 125c. device tested with high reliability test flow. 2 packing option C = standard packing tube t = tape and reel packing plating technology p or g = rohs compliant lithography b = 110nm technology, fab 2 diffusion plant automotive grade a = automotive: C40c to 85c part. only with temperature grade 6. device tested with high reliability test flow. 2 C = automotive: C40c to 125c. only with temperature grade 3. notes: 1. maximum frequency device operation in the extended vcc range (2.3v to 2.7v) is only on the 40 mhz device. 2. micron recommends the use of the automotive grade device in the automotive environ- ment, autograde 6 and grade 3. micron m25p40 serial flash embedded memory device ordering information pdf: 09005aef8456654f m25p40.pdf - rev. y 8/12 en 55 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. revision history rev. y C 8/12 ? updated command set to include release from deep power-down. ? updated memory map to eliminate the 64kb block box. rev. x C 04/12 ? updated dimensions for mb package in the part number information scheme table in device ordering information. ? in signal names table, changed direction column for dq0 and dq1 to input and out- put respectively. ? changed the write disable command sequenced graphic. ? revised write status register topic. ? revised power-up/down and supply line decoupling topic. ? revised dfn8 6mm x 5mm package figure. rev. w C 03/12 ? updated dimensions for mc package in the part number information scheme table in device ordering information. rev. v C 02/12 ? corrected error in so8n package drawing. rev. u C 09/2011 ? applied micron branding. rev. 20.0 C 04/2010 ? corrected package nomenclature. rev. 19.0 C 02/2010 ? added the following package information: ufdfpn8 (mlp8) 4mm x 3mm and ufdfpn8 (mlp8) 2mm x 3mm. rev. 18.0 C 05/2009 ? revised cross-references. rev. 17.0 C 02/2009 ? table 8: vwi min (grade 3) = 1v versus 2.1v or (remove one row and grade indication). ? table: erase/program cycles = 100,000 cycles also for grade 3 (instead of 10,000). ? table: i cc3 operating current (read) change on test condition section as follows: old: c = 0.1v cc / 0.9v cc at 40 mhz and 75 mhz, q = open; new: c = 0.1v cc / 0.9v cc at 40 mhz, 50 mhz and 75 mhz, q = open; old: c = 0.1v cc / 0.9.v cc at 25 mhz, q = open; new: c = 0.1v cc / 0.9v cc at 25 mhz and 33 mhz, q = open. micron m25p40 serial flash embedded memory revision history pdf: 09005aef8456654f m25p40.pdf - rev. y 8/12 en 56 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. ? table: i cc3 operating current (read) change on test condition section as follows: old: c = 0.1v cc / 0.9v cc at 25 mhz, q = open; new: c = 0.1v cc / 0.9v cc at 25 mhz and 75 mhz, q = open; old: c = 0.1v cc / 0.9v cc at 20 mhz, q = open; new: c = 0.1v cc / 0.9v cc at 20 mhz and 33 mhz, q = open. ? table 15: valid also for grade 3: old: instruction times, process technology 110nm (device grade 6); new: instruction times, process technology 110nm. ? table 16: valid also for grade 3: old: instruction times, process technology 150nm (device grade 6); new: instruction times, process technology 150nm. ? table 17: deleted. ? table 19: added the following to the table head: "identified with device belonging to x technology version; changed t res1 = 30us and t res2 = 30us (removed 3us and 1.8us and note 5). rev. 16.0 C 10/2008 ? changed frequency up to 75 mhz (only in the standard v cc range). ? added new packages. ? added uid/cfd protection. ? extended v cc range to 2.3v. rev. 15.0 C 12/2007 ? applied numonyx branding. rev. 14.0 C 06/2007 ? modified the note below table 13. ? changed test condition for i cc3 in table 14. ? changed clock frequency, from 20 to 25 mhz, in table 20 and table 21. rev. 13.0 C 05/2007 ? 40 mhz operation added (see table: ac characteristics (*40 mhz operation, device grade 6, v ccmin = 2.3v.) ? removed the note below table 10. ? removed table: ac characteristics (33 mhz operation, device grade 6, v ccmin n =2.3v). rev. 12.0 C 01/2007 ? v cc voltage range from w17 2007 is extended to 2.3v to 3.6v. ? added table: ac characteristics (33 mhz operation, device grade 6, v ccmin =2.3v). ? ac characteristics at 40 mhz removed. rev. 11.0 C 12/2006 ? hardware write protection feature added to cover; small text changes to cover. ? added sections on v cc supply voltage and v ss ground. ? revised figure: bus master and memory devices on the spi bus. ? wip bit behavior specified at power-up in power-up and power-down section. ? revised table: absolute maximum ratings and v io maximum. micron m25p40 serial flash embedded memory revision history pdf: 09005aef8456654f m25p40.pdf - rev. y 8/12 en 57 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. ? vfqfpn8 package specifications updated. rev. 10.0 C 06/2006 ? t res1 and t res2 parameter timings changed for devices produced with the /x process technology. ? so8 narrow package specifications updated. rev. 9.0 C 04/2006 ? data contained in table 12 and table 19 is no longer preliminary. ? modified figure: bus master and memory devices on the spi bus. ? 40 mhz frequency condition modified for i cc3 in table: dc characteristics (device grade 3). ? condition changed for the data retention parameter in table: data retention and en- durance. ? vwi parameter for device grade 3 added to table: power-up timing and vwi thresh- old. ? so8 package specifications updated. ? /x process added to table: ordering information scheme. rev. 8.0 C 12/2005 ? note 2 added below figure 26 and note 3 added below figure 29. ? t res1 and t res2 modified in table 20: ac characteristics (50 mhz operation, device grade 6, v ccmin = 2.7v). ? read identification (rdid) added. titles of figure 29 and table 26 corrected. rev. 7.0 C 10/2005 ? 50 mhz operation added. ? all packages are rohs-compliant. blank option removed from under plating technol- ogy in table: ordering information scheme. ? mlp package renamed as vfqfpn, silhouette and package mechanical drawing up- dated. rev. 6.0 C 08/2005 ? updated page program commands under heading, "page programming, page pro- gram, instruction times, process technology 110nm." rev. 5.0 C 01/2005 ? minor text changes. ? notes 2 and 3 removed from table: ordering information scheme. ? end timing line of t shqz modified in figure: output timing. rev. 4.0 C 08/2004 ? device grade information clarified. ? data-retention measurement temperature corrected. micron m25p40 serial flash embedded memory revision history pdf: 09005aef8456654f m25p40.pdf - rev. y 8/12 en 58 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. ? details of how to find the date of marking added. rev. 3.0 C 03/2004 ? automotive range added. ? soldering temperature information clarified for rohs-compliant devices. rev. 2.0 C 11/2003 ? table of contents, warning about exposed paddle on mlp8, and pb-free options add- ed. ? change of naming for vdfpn8 package. ? 40 mhz ac characteristics table included as well as 25 mhz. i cc3max , t se (typ) and t be (typ) values improved. rev. 1.0 C 06/2003 ? initial data sheet release. 8000 s. federal way, p.o. box 6, boise, id 83707-0006, tel: 208-368-3900 www.micron.com/productsupport customer comment line: 800-932-4992 micron and the micron logo are trademarks of micron technology, inc. all other trademarks are the property of their respective owners. this data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. although considered final, these specifications are subject to change, as further product development and data characterization some- times occur. micron m25p40 serial flash embedded memory revision history pdf: 09005aef8456654f m25p40.pdf - rev. y 8/12 en 59 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. |
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